1. Field of the Invention
The invention in general relates to ferroelectric electronic memories and more particularly to such a memory in which the electronic signal output by the memory is independent of the history of the ferroelectric material.
2. Statement of the Problem
It is well-known that ferroelectric materials are capable of retaining a polarization which can be used to store information in a non-volatile memory. For example, if a strong enough electric field or voltage is placed across a ferroelectric capacitor, when the voltage is removed, a polarization in the direction of the field remains. If the field is then placed across the same capacitor in the opposite direction, the ferroelectric material switches, and when the field is removed, a polarization in the opposite direction remains. Electronic circuits have been designed to associate the polarization in one direction with a digital logic "1" state, and polarization in the opposite direction with a logic "0" state. See, for example, the circuits described in U.S. Pat. No. 2,876,436 issued to J. R. Anderson; U.S. Pat. No. 5,029,128 issued to Haruki Toda; and U.S. Pat. No. 5,406,510 issued to Takashi Mihara, et. al. These circuits include memory cells arranged in rows and columns, each memory cell including at least one switch and a capacitor having a pair of electrodes, and the memory also including plate lines connected to one electrode of the capacitor in each cell and bit lines connected to the other electrode of the capacitor through the switch. In the latter two patents the switch is a transistor having a gate and a pair of source/drains, and the memory further includes word lines connected to the control gate of the transistors. In the latter two patents, information is written into a memory cell by placing either a high or a low voltage on the bit line, turning the transistor on to connect the bit line to the capacitor, and placing a predetermined voltage between the high and low voltage on the plate line. The high voltage causes the memory cell to assume one polarization state, and the low voltage causes the memory cell to assume the opposite polarization state. The memory cell is read by creating a voltage difference between the bit line and plate line, connecting the bit line to the capacitor via the transistor. If the ferroelectric state changes due to the applied voltage, the bit line will assume a first voltage, and if the ferroelectric state does not switch, then the bit line will assume a second voltage. The bit line voltage is compared to a reference voltage that is about half-way between the first and second voltages; if the bit line voltage is below the reference voltage, a sense amp drives an output low, and if the bit line voltage is above the reference voltage, a sense amp drives an output high. In this way, the state of the ferroelectric capacitor prior to reading determines the output state when the cell is read.
Up until recently, all ferroelectric materials tended to fatigue over time, and the switching charge decreased to a point where the cell could no longer be read. Recently, a class of materials, called layered superlattice compounds herein, have been discovered that do not fatigue. However, while the switching charge remains relatively stable in these materials, there still remains a problem that the magnitude of the first and second voltages generally depends on the history of the memory cell. That is, depending on the history, both the first and second voltages in one reading on a specific cell will differ by voltage factor from the first and second voltages of a later reading of the same cell. For example, the hysteresis (polarization versus voltage) curve may drift over time in the order of milliseconds due to redistribution of charge within the capacitor. Thus, while the reference voltage will be between the first and second voltages for one reading, in a later reading both the first and second voltages may be above the reference voltage. This generally results in a misreading of the memory cell.
One solution to the above problem is disclosed in U.S. Pat. No. 4,888,733 issued to Kenneth J. Mobley on Dec. 19, 1989. The memory disclosed in the Mobley patent pulses the ferroelectric capacitor in one direction and stores the developed charge on a first temporary storage capacitor, pulses the ferroelectric capacitor in the opposite direction and stores the developed charge on a second temporary storage capacitor, and then compares the stored charges on the two storage capacitors. Thus, this memory is, in effect, self-referencing, since it does not require a separate reference potential. However, this solution significantly increases the length of time it takes to read a memory; thus, this memory is not competitive with state-of-the-art memories which require fast read times. Further, the memory cell layout is larger than that of other prior art memory cells, so a memory according to the Mobley design is relatively bulky and is not competitive in a memory market where memory chip are increasingly more dense. A ferroelectric memory that is self-referencing and also is competitive with state-of-the-art memories with respect to read time and density of the memory chip would be highly desirable.
3. Solution to the Problem
The present invention is a significant improvement over the prior art by providing a ferroelectric memory which develops a reference charge from which is subtracted the charge created on the plate line when the ferroelectric capacitor is read by placing a field across it. The following two benefits result: 1) a smaller memory cell; and 2) faster operation.
A second switching device in each memory cell is not required as in the Mobley cell since the voltage excursion of the plate line is not enough to significantly disturb deselected ferroelectric capacitors sharing that plate line. The result is a one-transistor-one-capacitor memory cell which lays out much smaller than the Mobley cell. A smaller memory cell, results in a smaller die size and reduced manufacturing cost.
The second major benefit of the invention is a streamlined read operation which reduces the time required for a read cycle. The Mobley invention requires the following sequence to develop a read charge:
1) the first bit line is driven from a low to a high and back to a low voltage; PA1 2) the resulting signal on the second bit line is stored on a first capacitor and isolated from the second bit line; PA1 3) the second bit line is driven from a low to a high and back to a low voltage; and PA1 4) the resulting signal on the first bit line is stored on a second capacitor and isolated from the first bit line.
The present invention only requires one line being driven from a starting voltage level to a high, then low, and then back to the starting level. This produces the read signal minus the reference signal on the plate line.
The read voltage signal is generated from a read charge, which charge is shared between the capacitance of one plate line and the ferroelectric capacitance. The reference voltage signal is generated by fully switching the same ferroelectric capacitor. The resulting charge is shared between the capacitance of the two plate lines and the ferroelectric capacitance.
The invention provides a ferroelectric integrated circuit memory comprising: a memory cell comprising a ferroelectric memory element; a first conducting line electrically connected to or electrically connectable to the ferroelectric memory element; a second conductor connected to or electrically connectable to the ferroelectric memory element; a third conducting line; a line driver for driving the first conductor to place a first field across the ferroelectric element and a second field across the ferroelectric memory element, the first and second electric fields being in opposite directions; a unity gain amplifier for driving the third conductor to the same voltage as the second conductor; a switch for connecting the second conducting line and the third conducting line; and a signal generator for generating timing signals and applying the timing signals to the line driver, the unity gain amplifier and the switch in timed sequence. Preferably, the ferroelectric element is a ferroelectric capacitor. Preferably, the memory includes a bit line, a first plate line connected to one electrode of the capacitor, and a transistor between the bit line and the other electrode of the capacitor, the first conducting line comprises the bit line, and the second conducting line comprises the plate line. Preferably, the third conducting line comprises a second plate line complementary to the first plate line. Preferably, the memory includes a first bit line, a plate line connected to one electrode of the capacitor, and a transistor between the bit line and the other electrode of the capacitor, the first conducting line comprises the plate line, and the second conducting line comprises the first bit line. Preferably, the third conducting line comprises a second bit line complementary to the first bit line. The memory can have a folded architecture or an open architecture.
The invention also provides a method of reading a ferroelectric integrated circuit memory that includes a ferroelectric element, a first conducting line electrically connected or connectable to the ferroelectric element, a second conducting line electrically connected or connectable to the ferroelectric element, and a third conducting line, the method comprising the steps of: applying a first voltage to the first conducting line to develop a first corresponding voltage on the second conducting line; driving the third conducting line to a voltage essentially equal to the first corresponding voltage; connecting the second conducting line to the third conduting line; applying a second voltage the first conducting line to develop a second corresponding voltage on the second conducting line and the third conducting line; and sensing the second corresponding voltage to provide an output signal representative of the state of the ferroelectric element prior to the step of applying a first voltage. Preferably, the first voltage and the second voltage is less than one-half the supply voltage and the other of the first voltage and the second voltage is greater than the supply voltage. Preferably, the ferroelectric element is a capacitor, the step of applying a first voltage creates a first electric field across the capacitor, and the step of applying a second voltage creates a second electric field across the capacitor, the second electric field opposite in direction to the first electric field.
In another aspect, the invention provides a method of reading a ferroelectric integrated circuit memory, the memory including a ferroelectric element and the method comprising the steps of: applying a first electric field across the ferroelectric element to develop a first charge on a conducting line, the first charge including either: the switching charge developed when the ferroelectric element switches in response to the first electric field applied across the ferroelectric element, or the non-switching charge developed when the first electric field is placed across the ferroelectric element and the ferroelectric element does not switch; applying a second electric field across the ferroelectric element to develop a second charge on the conducting line, the second electric field essentially equal to and opposite in direction to the first electric field, and the second charge equal to essentially one-half the charge developed when the ferroelectric element switches from full polarization in one direction to full polarization in the opposite direction in response to the second electric field; permitting a voltage to develop on the line as a result of the first and second charges; and sensing the voltage with a sense amp to produce an output voltage indicative of the polarization state of the ferroelectric element prior to placing the first and second fields across the ferroelectric element. Preferably, the memory includes a third conducting line and the step of developing the second charge includes the step of connecting the first conducting line to the third conducting line. Preferably, the memory includes a third conducting line and the step of developing the second charge includes the step of developing a charge on the third conducting line that is essentially equal to the first charge.
In yet another aspect, the invention provides a method of reading a ferroelectric integrated circuit memory, the memory including a ferroelectric element capable of being in a first polarization state and a second polarization state, a conducting line electrically connected or connectable to the ferroelectric element, and a power supply providing a supply voltage of Vcc, the method comprising the steps of: applying a first electric field and a second electric field to the ferroelectric element to develop a voltage on the conducting line, the second electric field in a direction opposite to the first electric field, and the developed voltage being greater than one-half Vcc if the ferroelectric memory is in the first polarization state prior to the application of the first and second electric fields and the developed voltage being less than one-half Vcc if the ferroelectric element is in the second polarization state prior to the application of the first and second electric fields; and using a sense amplifier to compare the developed voltage with a voltage equal to one-half Vcc to produce an output voltage indicative of the state of the ferroelectric element prior to placing the first and second fields across the ferroelectric element. Preferably, the ferroelectric element is a capacitor, the memory includes a bit line and a plate line, and the conducting line comprises the plate line. Preferably, the ferroelectric element is a capacitor, the memory includes a bit line and a plate line, and the conducting line comprises the bit line.
In still another aspect the invention provides a method of reading a ferroelectric integrated circuit memory, the memory including a ferroelectric element capable of being in a first polarization state and a second polarization state, a conducting line electrically connected or connectable to the ferroelectric element, the method comprising the steps of: developing a voltage on the conducting line by applying a first electric field and a second electric field to the ferroelectric element, the second electric field in a direction opposite to the first electric field; and sensing the developed voltage with a sense amplifier to produce an output voltage indicative of the state of the ferroelectric element prior to placing the first and second fields across the ferroelectric element. Preferably, the step of developing comprises changing the capacitance of the conducting line between the application of the first electric field and the application of the second electric field. Preferably, the ferroelectric element is a capacitor, the memory includes a bit line and a plate line. and the conducting line comprises the plate line. Preferably the ferroelectric element is a capacitor, the memory includes a bit line and line, and the conducting line comprises the bit line.
The memory according to the invention not only is effective and reliable even when the ferroelectric polarizability drifts over time, but the memory is competitively dense and fast. Numerous otherfeatures, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.